Electronic design automation industry

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The VLSI was an important pioneer in the electronic design automation industry. The “lambda-based” design style which was advocated by carver mead and Lynn Conway offered a refined packages of tools..

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VLSI became the early hawker of standard cell (cell-based technology). Rapid advancement in VLSI technology has lead to a new paradigm in designing integrated circuits where a system-on-a-chip (SOC) is constructed based on predesigned and pre-verified cores such as CPUs, digital signals processors, and RAMs. Testing these cores requires a large amount of test data which is continuously increasing with the rapid increase in the complexity of SOC. Test compression and compaction techniques are widely used to reduce the storage data and test time by reducing the size of the test data.

The Very large scale integration design or manufacturing of extremely small uses complex circuitry of modified semiconductor material.

In 1959- jack St. Claire Kilby (Texas instruments) – they developed the first integrated circuit of 10 components on 9 mm2. In 1959, Robert Norton Noyce (founder, Fairchild semiconductor) has improved this integrated circuit which has been developed by Jack St & Claire Kilby, in 1968- Noyce, Gordon E. Moore found Intel, in 1971- Ted Hoff (Intel) – has developed the first microprocessor (4004) consists of 2300 transistors on 9 mm2, since then the continuous improvement in technology has allowed for increased performance as predicted by Moore’s law.

The rate of development of VLSI technology has historically progressed hand-in-hand with technology innovations. Many conventional VLSI systems as a result have engendered highly specialized technologies for their support. Most of the achievements in dense systems integration have derived from scaling in silicon VLSI process. As manufacturing has improved, it has become more cost-effective in many applications to replace a chip set with a monolithic IC: package costs are decreased, interconnect path shrink, and power loss in I/O drivers is reduced. As an example consider integrated circuit technology: the semi conductor industry Association predicts that, over the next 15 years, circuit technology will advance from the current four metallization layers up to seven layers. As a result, the phase of circuit testing in the design process is moving to the head as a major problem in VLSI design. In fact, Kenneth M, Thompson, vice president and general manager of the Technology, Manufacturing, and Engineering Group for Intel Corporation, states that a major falsehood of testing is that “we have made a lot progress in testing” in reality it is very difficult for testing to keep speed with semi conductor manufacturing technology.

Today’s circuits are expected to perform a very broad range of functions as it also meets very high standards of performance, quality, and reliability. At the same time practical in terms of time and cost.

1.1 Analog & Digital Electronics

In science, technology, business, and, in fact, most other fields of endeavor, we are constantly dealing with quantities. In the most physical systems, quantities are measured, monitored, recorded, manipulated, arithmetically, observed. We should be able to represent the values efficiently and accurately when we deal with various quantities. There are basically two ways of representing the numerical value of quantities: analog and digital

1.2 Analog Electronics

Analogue/Analog electronics are those electronic systems with a continuously variable signal. In contrast, two different levels are usually taken in digital electronics signals. In analog representation a quantity is represented by a voltage, current, or meter movement that is comparative to the value of that quantity. Analog quantities such as those cited above have n important characteristic: they can vary over a continuous range of values.

1.3 Digital Electronics

In digital representation the quantities are represented not by proportional quantities but by symbols called digits. As an example, consider the digital watch, which provides the time of day in the form of decimal digits which represent hours and minutes (and sometimes seconds). As we know, the time of day changes continuously, but the digital watch reading does not change continuously; rather, it changes in steps of one per minute (or per second). In other words, this digital representation of the time of day changes in discrete steps, as compared with the representation of time provided by an analog watch, where the dial reading changes continuously.

Digital electronics that deals with “1s and 0s”, but that’s a vast oversimplification of the in and outs of going digital. Digital electronics operates on the premise that all signals have two distinct levels. Certain voltages might be the levels near the power supply level and ground depending on the type of devices used. The logical meaning should not be mixed with the physical signal because the meaning of this signal level depends on the design of the circuit. Here are some common terms used in digital electronics:

  • Logical-refers to a signal or device in terms of its meaning, such as “TRUE” or “FALSE”
  • Physical-refers to a signal in terms of voltage or current or a device’s physical characteristics
  • HIGH-the signal level with the greater voltage
  • LOW-the signal level with the lower voltage
  • TRUE or 1-the signal level that results from logic conditions being met
  • FALSE or 0-the signal level that results from logic conditions not being met
  • Active High-a HIGH signal indicates that a logical condition is occurring
  • Active Low-a LOW signal indicates that a logical condition is occurring
  • Truth Table-a table showing the logical operation of a device’s outputs based on the device’s inputs, such as the following table for an OR gate described as below

1.4 Number Systems

Digital logic may work with “1s and 0s”, but it combines them into several different groupings that form different number systems. Most of are familiar with the decimal system, of course. That’s a base-10 system in which each digit represents a power of ten. There are some other number system representations,

  • Binary-base two (each bit represents a power of two), digits are 0 and 1, numbers are denoted with a ‘B’ or ‘b’ at the end, such as 01001101B (77 in the decimal system)
  • Hexadecimal or ‘Hex’-base 16 (each digit represents a power of 16), digits are 0 through 9 plus A-B-C-D-E-F representing 10-15, numbers are denoted with ‘0x’ at the beginning or ‘h’ at the end, such as 0x5A or 5Ah (90 in the decimal system) and require four binary bits each. A dollar sign preceding the number ($01BE) is sometimes used, as well.
  • Binary-coded decimal or BCD-a four-bit number similar to hexadecimal, except that the decimal value of the number is limited to 0-9.
  • Decimal-the usual number system. Decimal numbers are usually denoted by‘d’ at the end, like 24d especially when they are combined with other numbering systems.
  • Octal-base eight (each digit represents a power of 8), digits are 0-7, and each requires three bits. It is rarely used in modern designs.

1.5 Digital Construction Techniques

Building digital circuits is somewhat easier than for analog circuits-there is fewer components and the devices tend to be in similarly sized packages. Connections are less susceptible to noise. The trade-off is that there can be many connections, so it is easy to make a mistake and harder to find them. There are a few visual clues as result of uniform packages.

1.5.1 Prototyping Boards

Prototypes is nothing but putting together some temporary circuits, or, as part of the exercises using a common workbench accessory known as a prototyping board. A typical board is shown in Figure 1 with a DIP packaged IC plugged into the board across the centre gap. This board contains sets of sockets in rows which are connected mutually for the component leads to be connected and plugged in without soldering. Apart from these outer edges of the board which contains long rows of sockets are also connected together so that they can be used for ground connections and power supply which are common to most components.

Assembling wiring layout on the prototype board should be carried out systematically, similar to the schematic diagram shown.

1.5.2 Reading Pin Connections

IC pins are almost always arranged so that pin 1 is in a corner or by an identifying mark on the IC body and the sequence increases in a counter-clockwise sequence looking down on the IC or “chip” as shown in Figure 1. In almost all DIP packages, the identifying mark is a dot in the corner marking pin 1. Both can be seen in the diagram, but on any given IC only one is expected to be utilised.

1.5.3 Powering Digital Logic

Where analog electronics is usually somewhat flexible in its power requirements and tolerant of variations in power supply voltage, digital logic is not nearly so carefree. Whatever logic family you choose, you will need to regulate the power supply voltages to at least ±5 percent, with adequate filter capacitors to filter out sharp sags or spikes.

To provide references to the internal electronics that sense the low or high voltages and also act on them as logic signals, the logic devices rely on stable power supply voltages. The device could be confused and also misinterpret the inputs if the device’s ground voltage is kept away from 0 volts, which in turn causes temporary changes in the signals, popularly known as glitches. It is better to ensure that the power supply is very clean as the corresponding outcome can be very difficult to troubleshoot. A good technique is to connect a 10 ~ 100 µF electrolytic or tantalum capacitor and a 0.1 µF ceramic capacitor in parallel across the power supply connections on your prototyping board.



As a background research, recent work on iterative circuits was investigated. In this section, seven main proposals from the literature will be reviewed. The first paper by Douglas Lewin published in (1974, pg.76,277), titled – Logic Design of Switching Circuits, in this book he states that quite often in combinational logic design, the technique of expressing oral statements for a logic circuit in the form of a truth table is inadequate. He stated that for a simple network, a terminal description will often suffice, but for more complex circuits, and in particular when relay logic is to be employed, the truth table method can lead to a laborious and inelegant solution.

2.1 Example:

A logic system could be decomposed into a number identical sub-systems, then if we could produce a design for the sub-system, or cell, the complete system could be synthesized by cascading these cells in series. The outputs of one cell form the inputs to the next one in the chain and so on, each cell is identical except for the first one (and frequently he last one) whose cell inputs must be deduced from the initial conditions. Each cell has external inputs as well as inputs from the preceding cell, which are distinguished by defining the outputs of a cell as its state. Figure 2.1 – Iterative Switching Systems

The second proposal which will b reviewed was presented by Fredrick J. Hil and Gerald R. Peterson published in (1981, pg. 570), titled – Introduction to Switching Theory and Logic Design, in this book, they discussed that iterative network is highly repetitive form of a combinational logic network. The repetitive structure make possible to describe the iterative networks utilizing techniques that already developed for sequential circuits, the author in this books he has limited his discussion to one dimensional iterative networks represented by the cascade or identical cells given in below figure. A typical cell with appropriate input and output notation is given in one more figure below (b). Now note the two distinct types of inputs, i.e., primary inputs from the outside world and secondary inputs from the previous cell in the cascade. And similarly and there are two types of outputs, i.e., primary to the outside world and secondary to the next cell in the cascade. The boundary inputs which are at the left of the cascade denoted by us in the same manner as secondary inputs. At some cases the inputs will be constant values.

A set of boundary inputs emerges from the right most cell in the cascade. although these outputs are to the outside world, they will be labelled in the same manners secondary outputs. The boundary outputs will be the only outputs of the iterative networks.

The third proposal by Barri Wilkinson with Raffic Makki, published in (1992, pg. 72-4) titled -digital design principles, in this book, they discussed about the design and problems of iterative circuits and stated that, there are some design problems which would require a large number of gates if designed as two level circuits. On approach i.e., is to divide each function into a number of identical sub functions which need be performed in sequence and the result of one sub function is used in the next sub function. A design based around the iterative approach is shown in below figure. There are seven logic circuit cells each cell accepts one code word digit and the output from the preceding cell. The cell produces one output, Z, which is a 1 whenever the number of 1’s on the two inputs is odd. Hence successive outputs are a 1 when the number of 1’s on inputs to that point is odd and the final output is a 1 only when the number of 1’s in the whole code word is odd as required.

To create an iterative design, the number of cells and the number of data inputs to each cell need to be determined and also the number of different states that must be recognized by the cell. The number of different states will define the number of lines to the next cell (usually carrying binary encoded information).

The fourth proposal was reviewed by Douglas Lewin and David Protheroe published in (1992, pg. 369),titled – Design of Logic systems, in this book, according to them, iterative networks were widely used in the early days of switching systems when relays were the major means of realizing logic circuits. these technique fell into disuse when electronic logic gates widely available. It is possible to implement an arbitrary logic function in the form of an iterative array, the technique is most often applied to functions which are in the sense ‘regular’ in that the overall function may be achieved by performing the same operation up to a sequence of a data bits. Iterative cell techniques are particularly well suited to pattern recognition and encoding and decoding circuits with large numbers of parallel inputs.

The method is also directly applicable to the design of VLSI circuits and has the advantage of producing a modular structure based on a standard cell which may be optimized independently in terms of layout etc. Circuits containing any number of input variables can easily be constructed by simply extending the network with more cells. they examine the iterative circuits with some examples, although it is possible to implement an arbitrary logic function in the form of an iterative array, the technique is most often applied to functions which are in this sense ‘regular’ in that the overall function may be achieved by performing the same operation upon a sequence of data bits.

Suppose a logic system could be decomposed into a number of identical subsystems; then if we could produce a design for the subsystem, or cell, the complete system could be synthesized by cascading these cells in series. Problem Reduced: this problem now has been reduced to that of specifying and designing the cell, rather than the complete system.

The fifth proposal presented by Brians Holdsworth published in (1993, pg. 165-166) titled – Digital Logic Design, stated that iterative networks widely used before the introduction of electronic gates are again of some interest to the logic designers as a result of developments in semiconductor technology. Moss pass transistors which are easily fabricated are used in LSI circuits where these LSI circuits require less space and allow higher packing densities. One of the major disadvantages of hard-wired iterative networks was the long propagation delays because of the time taken for signals to ripple through a chain of iterated cells. This is no longer such a significant disadvantage since of the length of the signal paths on an LSI chip are much reduced in comparison with the hard-wired connections between SSI and MSI circuits. However, the number of pass transistors that can be connected in series is limited because of signal degradation and it is necessary to provide intercell buffers to restore the original signal levels. One additional advantage is the structural simplicity and the identical nature of the cells which allows a more economical circuit layout.

A book proposed by Brians Holdsworth and R.C. Woods published in (2002, pg.135), titled – Digital Logic Design, in this book, the discussion on the structure has made and stated that iterative network consists of number of identical cells interconnected in a regular manners as shown in figure with the variables X1……….Xn are termed as primary input signals while the output signals termed as Z1……………Zn and another variable is also taken a1…………an+1 are termed as secondary inputs or outputs depending on whether these signals are entering or leaving a cell. The structure of an iterative circuit may be defined as one which receives the incoming primary data in parallel form where each cell process the incoming primary and secondary data and generates a secondary output signal which is transmitted to the next cell. Secondary data is transmitted along the chain of cells and the time taken to reach steady state is determined by the delay times of the individual cells and their interconnections.

According to Larry L. Kinney, Charles .H and Roth. JR, published in (2004, pg.519) titled – Fundamentals of Logic design, in this book they discussed that many design procedures used for sequential circuits can be applied to the design of the iterative circuits, they consists of number of identical cells interconnected in a regular manner. Some operations such as binary addition, naturally lend themselves to realization with an iterative circuit because of the same operation is performed on each pair input bits. The regular structure of an iterative circuit makes it easier to fabricate in integrated circuit from than circuits with less regular structures, the simplest form of a iterative circuit consists of a linear array of combinational cells with signals between cells travelling in only one direction, each cell is a combinational circuit with one or more primary inputs and possibly one or more primary outputs. In addition, each cell has one or more secondary inputs and one or more secondary outputs. Then the produced signals carry information about the “state” of one cell to the next cell. The primary inputs to the cells are applied in parallel; that is, they are applied at the same time, the signals then propagate down the line of cells. Because the circuit is combinational, the time required for the circuit to reach a steady- state condition is determined only by the delay times of the gates in the cell. As soon as steady state is reached, the output may be read. Thus, the iterative circuits can function as a parallel- input, parallel-output device, in contrast with the sequential circuit in which the input and output are serial. One can think of the iterative circuits as receive its inputs as a sequence in time.

Example: parallel adder is an example of iterative circuits that has four identical cells. The serial adder uses the same full adder cell as he parallel adder, but it receives its inputs serially and stores the carry in a flip-flop instead of propagating it from cell to cell.

The final proposal was authored by JOHN F WAKERLY, published in (2006, pg. 459, 462, 756), titled – Digital Design Principles, in this book he quoted that, iterative circuits is a special type of combinational circuits, with the structure shown in below figure. This circuit contains n identical modules, each of which contains both primary inputs and primary outputs and cascading inputs and cascading outputs. The left most cascading inputs which is shown in below figure are called boundary inputs and are connected to fixed logic values in most iterative circuits. The right most cascading outputs are called boundary outputs and these cascading output provides important information. Iterative circuits are well suited to problems that can be solved by a simple iterative algorithm:

  1. Set C0 to its initial value and set i=0
  2. Use Ci and Pli to determine the values of P0i and Ci+1.
  3. Increment i.
  4. If i restore.

    Xilinx ISE project navigator:

    Xilinx ISE consists of an array of software tools; we illustrate the basic development process. Four major steps include:

    1. Create the project design and HDL codes.
    2. Create a test bench and perform RTL simulation
    3. Adding a constraint file and to synthesize and implement the code.
    4. Generate and download the configuration file to an FPGA device.

    7.14 Overview of ISE Tool

    ISE controls all aspects of the design flow. Through the Project Navigator interface, can access all of the design entry and design implementation tools. You can also access the files and documents associated with your project. Project Navigator maintains a flat directory structure; therefore, maintain revision control through the use of snapshots.

    7.14.1 Project Navigator Interface

    The Project Navigator Interface is divided into four main sub windows, as seen in below figure. On the top left is the Sources window which hierarchically displays the elements included in the project. Beneath the Sources window is the Processes window, which displays available processes for the currently selected source. The third window at the bottom of the Project Navigator is the Transcript window which displays status messages, errors, and warnings and also contains interactive tabs fo Tcl scripting and the Find in Files function. The fourth window to the right is a multi-document interface (MDI) window refered to as the Workspace. It enables you to view html reports, ASCII text files, schematics, and simulation waveforms. Each window may be resized, undocked from Project Navigator or moved to a new location within the main Project Navigator window. The default layout can always be restored by selecting View > Restore Default Layout. These windows are discussed in more detail in the following sections.

    7.14.2 Sources Window

    This window consists of three tabs which provide information for the user. Each tab is discussed in further detail below.

    7.14.3 Sources Tab

    The Sources tab displays the project name, the specified device, and user documents and design source files associated with the selected Design View. The Design View (“Sources for”) drop-down list at the top of the Sources tab allows you to view only those source files associated with the selected Design View, such as Synthesis/Implementation standards.

    7.14.4 Devices in the Spartan-3 Subfamily

    Even though Spartan-3 FPGA devices has similar types of logic cells and macro cells, their densities differ. Each subfamily contains an array of devices of various densities.

    7.14.5 Macro Cell

    The Spartan-3 device contains four types of macro blocks: combinational multiplier, block RAM, digital clock manager (DCM), and input/ output block (IOB). The combinational multiplier accepts two 18-bit numbers as inputs and calculates the product. The block RAM is an 18k-bit synchronous SRAM that can be arranged in various types of configurations. A DCM uses a digital-delayed loop to reduce clock skew and to control the frequency and phase shift of a clock signal. An IOB controls the flow of data between the device’s I/O pins and the internal logic. It can be configured to support a wide variety of I/O signalling standards.

    7.15 Development Flow

    The simplified development flow of an FPGA-based system is shown in below figure, to facilitate further reading, we follow the terms used in Xilinx documentation. The left portion of the flow is the refinement and programming process, in which a system is transformed from an abstract textual HDL description to a device cell-level configuration and then downloaded to the FPGA device. The right portion is the validation process, which checks whether the system meets the functional specification and performance goals. The major steps the flow are:

    1. Design the system and derive the HDL files(s). We may need to add a separate constraint file to specify certain implementation constraints.
    2. Develop the test bench in HDL and perform RTL simulation. The RTL term reflects the fact that the HDL code is done at the register transfer level.
    3. Perform synthesis and implementation. The synthesis process is generally know as logic synthesis, in which the software transforms the HDL constructs to generic gate level components, such as simple logic gates and FFs. The implementation process consists of three smaller processes: translate, map, and place and route.
    4. Translate: The translate process merges multiplies design files to a single netlist. MAP: This process which is generally known as technology mapping, maps the generic gates in the netlist to FPGAs logic cells and IOBs.

      PLACE and ROUTE PROCESS: which is generally known as placement and routing, it derives the physical layout inside the FPGA chip. It places the cells in physical locations and determines the routes to connect various signals. In Xilinx flow, static timing analysis, this static timing analysis determines various timing parameters, such as maximal propagation delay and maximal clock frequency, this is performed at the end of the implementation process

    5. Now at last generate and download the programming file. In this process, a configuration file is generated according to the final netlist. The file is downloaded to an FPGA device serially to configure the logic cells and switches. The physical circuit can verified consequently. The optional functional simulation can be performed after synthesis, and the optional timing simulation can be performed after implementation. Functional simulation uses a synthesized netlist to replace the RTL description and checks the corrections of the synthesis process. Timing simulations uses the final netlist, along with detailed timing data, to perform simulation. Because of the complexity of the netlist, functional and timing simulation may require a significant amount of time. If we follow good design and coding practices, the HDL code will be synthesized and implemented correctly. We only need to use RTL simulation to check the correctness of the HDL ode and use static timing analysis to examine the relevant timing information. Both functional and timing simulations can be omitted from the development flow.

    7.15.1 Snapshots Tab

    The Snapshots tab displays all snapshots associated with the project currently open in Project Navigator. A snapshot is a copy of the project including all files in the working directory, and synthesis and simulation sub-directories. A snapshot is stored with the project for which is was taken, and the snapshot can be viewed in the snapshots tab.

    7.15.2 Libraries Tab

    The Libraries tab displays all libraries associated with the project open in Project Navigator.

    7.15.3 Processes Window

    This window contains one default tab called the Processes tab.

    7.15.4 Processes Tab

    The Processes tab is context sensitive and changes based upon the source type selected in the Sources tab and the Top-Level Source Type in your project. From the Processes tab, run the functions necessary to define, run and view your design. The Processes tab provides access to the following functions:

    • Add an Existing Source
    • Create New Source
    • View Design Summary
    • Design Entry Utilities

    Provides access to symbol generation, instantiation templates, HDL Converter, View command line Log File, and simulation library compilation.

    7.15.5 User Constraints

    Provides access to editing location and timing constraints.

    7.15.6 Synthesis

    Provides access to Check Syntax, Synthesis, View RTL or Technology Schematic, and synthesis reports.

    7.15.7 Implement Design

    Provides access to implementation tools, design flow reports, and point tools.

    7.15.8 Generate Programming File

    Provides access to the configuration tools and bit stream generation. The Processes tab incorporates automake technology. This enables the user to select any process in the flow and the software automatically runs the processes necessary to get to the desired step. For example, when run the Implement Design process, Project Navigator also runs the Synthesis process because implementation is dependent on up-todate synthesis results.

    7.15.9 Transcript Window

    The Transcript window contains five default tabs: Console, Errors, Warnings, Tcl Console, Find in Files.

    7.15.10 Console

    Displays errors, warnings, and information messages. Errors are signified by a red (X) next to the message, while warnings have a yellow exclamation mark (!).

    7.15.11 Warnings

    Displays only warning messages. Other console messages are filtered out.

    7.15.12 Errors

    Displays only error messages. Other console messages are filtered out.

    7.15. 13 Tcl Console

    Is a user interactive console. In additions to displaying errors, warnings and informational messages, the Tcl Console allows a user to enter Project Navigator specific Tcl commands. For more information on Tcl commands, see the ISE Help.

    7.15.14 Find in Files

    Displays the results of the Edit > Find in Files function.

    7.16 Workspace

    7.16.1 Design Summary

    The Design Summary lists high-level information about project, including overview information, a device utilization summary, and performance data gathered from the Place & Route (PAR) report, constraints information, and summary information from all reports with links to the individual reports.

    7.16.2 Text Editor

    Source files and other text documents can be opened in a user designated editor. The editor is determined by the setting found by selecting Edit > Preferences, expand ISE General and click Editor. The default editor is the ISE Text Editor. ISE Text Editor enables to edit source files and user documents. You can access the Language Templates, which is a catalog of ABEL, Verilog and VHDL language, and User Constraints File templates that you can use and modify in your own design.

    7.16.3 ISE Simulator / Waveform Editor

    ISE Simulator / Waveform Editor is a test bench and test fixture creation tool integrated in the Project Navigator framework. Waveform Editor can be used to graphically enter stimuli and the expected response, then generate a VHDL test bench or Verilog test fixture.

    7.16.4 Schematic Editor

    The Schematic Editor is integrated in the Project Navigator framework. The Schematic Editor can be used to graphically create and view logical designs.



    This chapter review the major contributions of this thesis and discusses some directions for future research

    8.1 Dissertation Contributions

    Most of the test engineers and researchers are trying to discover extremely appropriate design of Iterative circuits schemes to maximise the test methodology. Usually, most of the inventions are providing enormous results and a number of well-known advantages, but always there is a question or the most important matter rose in development of designing of Iterative circuits; the reliability of iterative circuits. In this chapter, a brief review of the contributions of the dissertation is presented.

    In chapter 2, a review of iterative circuits and its investigated, as is well known, iterative networks were widely used in the early days of switching systems when relays were the major means of realizing logic circuits. Iterative cell techniques are particularly well suited to pattern recognition and encoding and decoding circuits with large numbers of parallel inputs. The method is also directly applicable to the design of VLSI circuits and has the advantage of producing a modular structure based on a standard cell which may be optimized independently in terms of layout etc.

    In chapter 3, an overview of design methods for iterative circuits are discussed quoted as a design methodology based on a cyclic process of prototyping, testing, analyzing, and refining a product or process. Changes and refinements are made, in the most recent iteration of a design, based on the results of testing. Iterative design process might be applicable in the entire new product development process. In the early stages of development changes are easy and affordable to implement. In the iterative design process the first is to develop a prototype. And also mentioned about the classification of iterative circuits with an example.

    8.2 Testability of Iterative Circuits

    The increase in the complexity of the integrated circuits and the inherent increase in the cost of the test carried out on them are making it necessary to look for ways of improving the testability of iterative circuits. However the results can be extended to stable class of bilateral circuits. Kautz proposed the cell fault model (CFM) which was adopted my most researchers in testing ILAs. As assumed by CFM only one cell can be faulty at a time. As long as the cell remains combinational, the output functions of the faulty cell could be affected by the fault.

    In chapter 4, the design of iterative building blocks are investigated through different binary arithmetic circuits as it is a combinatorial problem. For the binary arithmetic, it may seem insignificant to use the methods which we have already seen for designing combinatorial circuits to obtain circuits. But the problem persists with this so the general method to create these kinds of circuits would use too many gates. We must look for different routes. As well as the coding was also developed with the building blocks.

    In chapter 5, investigation on need for testing is made stating that as the density of VLSI products increases, their testing becomes more difficult and costly. Generating test patterns has shifted from a deterministic approach, in which a testing pattern is generated automatically based on a fault model and an algorithm, to a random selection of test signals. While most problems in VLSI design has been reduced to algorithm in readily available software, the responsibilities for various levels of testing and testing methodology can be significant burden on the designer. Manufacturing Test Principles A critical factor in all LSI and VLSI design is the need to incorporate methods of testing circuits. This task should proceed concurrently with any architectural considerations and not be left until fabricated parts are available. Optimal Testing With the increased complexity of VLSI circuits, testing has become more costly and time-consuming,

    In chapter 6, these chapter discusses about the Design and Implementation of Circuits on FPGA, based on VLSI Design so states that the design and implementation is based on two types ASIC and FPGA but in detail we discuss about the FPGA Historical Background and Review on FPGA states that In some FPGAs, two I/O cells can be combined to support differential pair I/O standards. A trend in FPGAs is to include cores for specialized functions such as single-port and dual-port RAMs, first-in-first-out (FIFO) memories, multipliers, and DSPs. Within any given FPGA, all memory cores are usually of the same size in terms of the total number of memory bits, but each memory cores in the arrays is individually programmable. We also discuss about the Implementation Styles, and example on FPGA, as well as Benefits of FPGA Technology, and also aroused a question about why choosing an FPGA, and the Software Development in FPGA technology and finally we end this chapter this Testing on FPGA.

    In chapter 7, A Review on Verilog was stated and also Basic concepts and also mentioned about the Hardware Description Language quotes that Two things distinguish an HDL from a linear language like “C”: Concurrency and Timing, as well as the introduction to Verilog was also discussed, combining with these discussion was also made on Features, Design Specification, Design Styles, Functional Verification and Testing, Logic synthesis, Floor Planning Automatic Place and Route, Physical Layout, Design Hierarchies, Modules, Instances, ports, Behavioural & RTL Modelling, Modelsim, Project flow, Commands, Graph Verifying, and finally discussed about the Xilinx ISE Tools, in this Xilinx ISE section we will clearly understand about the how to create a project, synthesis and implementation and finally errors, warnings and many more are found, in ISE simulator or waveform editor ISE Simulator / Waveform Editor is a test bench and test fixture creation tool integrated in the Project Navigator framework. Waveform Editor can be used to graphically enter stimuli and the expected response, then generate a VHDL test bench or Verilog test fixture. At last the chapter ends with the Schematic Editor that is integrated in the Project Navigator framework. The Schematic Editor can be used to graphically create and view logical designs



    • Rubio, R. Anglada, J. Figueras (1989), “Easily Testable Iterative Uni-dimensional CMOS Circuits”, European Test Conference, Volume. 12, Issue 14, p. 240 – 245.
    • Barry Wilkinson and Rafic Makki (1992), Digital System Design, 2nd Ed, Prentice Hall.
    • B. Holdsworth (1993), Digital Logic Design, 3rd Ed, Butterworth-Heinemann.
    • Brian Holdsworth and Clive Woods (2002), Digital Logic Design, 4th Ed, Newnes Publications.
    • D. D. Givone and R. P. Roesser (2006), “Multidimensional Linear Iterative Circuits—General Properties”, IEEE Journal on Computers, Volume: C-21, Issue: 10, p. 1067- 1073.
    • Douglas Lewin (1974), Logical Design of Switching Circuits, 2nd Ed, Thomas Nelson & Sons Ltd.
    • Douglas Lewin and David Protheroe (1994), Design of Logic Systems, 2nd Ed, Chapman & Hall.
    • Fredrick J. Hill and Gerald R. Peterson (1981), Introduction to Switching Theory & Logic Design, 3rd Ed, John Wiley & Sons, Inc.
    • H.Charles Roth, and L. Larry (2004) Kinney Fundamentals of logic design, 6th Ed, CENGAGE LEARNING.
    • Hassan A. Farhat (2004), Digital design and computer organization, CRC Press LLC.
    • John F. Walkerly (2006), Digital Design: Principles & Practices, 4th Ed, Prentice Hall.
    • John V. Oldfield and Richard C. Dorf (1995), Field Programmable Gate Arrays: Reconfigurab;e Logic for Rapid Prototyping and Implementation of Digital Systems, John Wiley & Sons, Inc.
    • Laung-Terng Wang, Charles E. Stroud, Nur A. Touba (2008), System-on-chip test architectures: nanometer design for testability, Elsevier Inc.
    • M. Morris Manoand Charles R. Kime (2004), Logic and Computer Design Fundamentals, 3rd Ed, Prentice Hall.
    • Pong P. Chu (2008), FPGA prototyping by VHDL examples: Xilinx Spartan, 3 version, John Wiley & Sons Inc.
    • R. C. Seals & G. F. Whapshott (1997), Programmable Logic: PLDs & FPGAs, 1st Ed, Macmillan Press Ltd.
    • Wai-Kai Chen (2003), VLSI technology, CRC Press LLC.

    9.1 Electronic References

    • https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1041811&isnumber=22329 (Accessed on 03/09/09).
    • https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1672046&isnumber=3064 (Accessed 15/09/09).
    • https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=36249&isnumber=1513 (Accessed on 15/09/09)
    • www.ece.ucdavis.edu/~halasaad/Data/vts93.pdf (Accessed on 20/09/09).
    • https://deepblue.lib.umich.edu/bitstream/2027.42/5024/4/bac2746.0001.001.txt(Accessed on 20/09/09).
    • www.csupomona.edu/~apfelzer/204pdf/204-9.pdf (Accessed on 24/09/09).
    • https://www.cogs.susx.ac.uk/users/adrianth/ecal95/img3.gif (Accessed on 24/09/09)
    • portal.acm.org/citation.cfm?id=1311977 (Accessed on 24/09/09).
    • www.mrc.uidaho.edu/mrc/people/jff/240/241/…/iterative.htm (Accessed on 24/09/09).
    • www.mrc.uidaho.edu/mrc/people/jff/240/241/…/iterative.htm (Accessed on 24/09/09).
    • ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=313328 (Accessed on 25/09/09).
    • www.cse.iitd.ernet.in/~mbala/csl316/slides/sec2.ppt (Accessed on 25/09/09).
    • citeseer.ist.psu.edu/102979.html (Accessed on 25/09/09).
    • www.freepatentsonline.com/3290624.html (Accessed on 27/09/09).
    • dtlab.kaist.ac.kr/…/Chap%2016%20-%20Sequential%20Ckt%20Design.pdf (Accessed on 27/09/09).
    • www.ece.ucdavis.edu/~halasaad/Data/vts93.pdf (Accessed on 29/09/09).
    • www.freepatentsonline.com/3290624.html (Accessed on 30/09/09).
    • dtlab.kaist.ac.kr/…/Chap%2016%20-%20Sequential%20Ckt%20Design.pdf (Accessed on 05/10/09).
    • www.ece.ucdavis.edu/~halasaad/Data/vts93.pdf (Accessed on 05/10/09).
    • https://www.authorstream.com/presentation/Niteesh-84640-vlsi-technology-entertainment-ppt-powerpoint/ (Accessed on 07/10/09).
    • https://www.cs.unm.edu/~melaniem/pdfs/Arora_SSISwarm_2009.pdf (Accessed on 07/10/09).
    • https://www.ece.northwestern.edu/~seda/eecs355_W07_lec01.pdf(Accessed on 14/10/09).
    • https://www.fpgacentral.com/docs/fpga-tutorial/fpga-design-flow-overview (Accessed on 14/10/09).
    • https://www.strumpen.net/xilinx/tut82i/ise.html (Accessed on 25/10/09).
    • https://i.ehow.com/images/GlobalPhoto/Articles/4839347/FullAdderNewProjectWizard_Full.jpg (Accessed on 25/10/09).
    • https://i.ehow.com/images/GlobalPhoto/Articles/4839347/FPGAsetting_Full.jpg (Accessed on 25/10/09).
    • https://i.ehow.com/images/GlobalPhoto/Articles/4839347/verilogmodule_Full.jpg (Accessed on 25/10/09).
    • https://i.ehow.com/images/GlobalPhoto/Articles/4839347/Synthesizer_Full.jpg (Accessed on 25/10/09).
    • https://i.ehow.com/images/GlobalPhoto/Articles/4839347/Halfadder_Full.jpg (Accessed on 25/10/09).

    CHAPTER 10

    10. Appendix

    10.1 ADDER x1

    10.2 ADDER x2

    10.3 Adder Sum

    10.4 Carry

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